The present invention relates generally to an integrated component and a method for controlling the electrical property of a passive device during the fabrication of the integrated component. More particularly, the present invention relates to a method for controlling the electrical property of the passive device by selecting at least one layout pattern of a later manufacturing process of the fabrication of the integrated component and the related structure of the integrated component.
Many electrical products have at least one integrated circuit (IC) chip inside for providing electricity control function. An IC chip may include many integrated components, such as logic circuits or active or passive devices. The electrical properties of all the devices of the integrated components are critical because they affect the performances of the IC chip. In mass production, when fabricating integrated components on a wafer, there are many factors that influence the stability of the electrical properties of the produced integrated components, such as process variation. For example, the process variation may occur when producing integrated component products with different tools or facilities. When process variation occurs, which bring unexpected variations of electrical properties of the produced integrated components, the performance of the product will be effected. Usually, the manufacturer can only throw away the products when the performance is beyond the standard. Or, before fabrication, the integrated components have to be over-designed in order to cover the process variation. In either way, the fabrication cost or the performance of the integrated components is sacrificed. Accordingly, it is still an issue for the manufacturer of integrated components and IC designer to improve the yield of integrated components or decrease the effect of process variation for reducing the fabrication cost and improving the performance.